Sort of. Down to around 14nm nodes, maybe lower, the number was the actual minimum length of the transistor gate. Somewhere thereabouts the transistors weren't shrinking as much but they needed the number to go down so it became some rough estimate of PPA (power performance area) improvement - it's not just density.
There's also a distinction between "drawn length" which is the number specified by the designer, and the actual feature size on silicon. This can be scaled up or down either completely arbitrarily (meaning the drawn length is a total sham) or optically (meaning the drawn length is real but the chip is fabricated with a magnification <1)
Oh no, long before 14nm. A quick google tells me that the gate pitch on Intel 14nm is 70nm!
Obviously there's a ton of complexity here and lots of cheats and optimizations were done over the decades that weren't directly related to linear sizing. But I stand behind the threshold I gave: the big discontinuity in the industry, where "node size" and "feature size" clearly began to significantly diverge, was the introduction of finfet/tri-gate transistors in Intel 32nm.
Gate pitch is not the same as gate length. The smallest feature size is usually the transistor gate length. In Samsung 14nm processes for example the drawn fin length is in fact 14nm. The actual physical size of the fin is closer to 8nm but I believe the whole structure is still close to 14.
The "divergence" started happening long before finfets where Intel is concerned, but they weren't manufacturing for anyone else. For the rest of the foundries, it still followed somewhat logically, if not exactly, down to 14 at least.
There's also a distinction between "drawn length" which is the number specified by the designer, and the actual feature size on silicon. This can be scaled up or down either completely arbitrarily (meaning the drawn length is a total sham) or optically (meaning the drawn length is real but the chip is fabricated with a magnification <1)